The present invention relates to a method for producing silicon epitaxial wafer, and epitaxial wafer produced by such method; and in particular to a method for producing silicon epitaxial wafer in which a silicon epitaxial layer is ion-implanted and is then stacked with another silicon epitaxial layer by vapor-phase growth, to thereby form a buried layer, and epitaxial wafer produced by such method.
Japanese Laid-Open Patent Publication 1-105557 discloses a technique in which an impurity element is introduced by ion implantation into a silicon single-crystalline thin film (simply referred to as xe2x80x9csilicon epitaxial layerxe2x80x9d, or more simply as xe2x80x9cepitaxial layerxe2x80x9d hereinafter) in a silicon epitaxial wafer (simply referred to as xe2x80x9cepitaxial waferxe2x80x9d hereinafter) which comprises a silicon single-crystalline substrate and such epitaxial layer formed thereon by the vapor-phase epitaxial growth process. The above publication also discloses process steps for fabricating a CMOS circuit in such epitaxial wafer.
In the fabrication of a vertical MOSFET or vertical bipolar transistor in the epitaxial wafer, it is sometimes necessary to form an impurity doped region having a large depth (which is referred to as xe2x80x9cvertical doped regionxe2x80x9d or xe2x80x9cvertical impurity-doped regionxe2x80x9d hereinafter in this specification). Such xe2x80x9cvertical doped regionxe2x80x9d is typified by a device isolation region for isolating a device from other region (device isolation regions 3, 4 in FIG. 1 of the above patent publication), and an impurity-doped region serving as a conduction route toward a high-density impurity diffused layer formed so as to be buried in the wafer (drain regions 6, 6a in FIG. 1 of the above patent publication).
For the case that the epitaxial layer is formed as a single layer having a relatively large thickness, it may be rather difficult to form a vertical doped region deep enough to penetrate the epitaxial layer only by a direct ion implantation. One technique for solving such problem is such that preliminarily forming an ion-implanted layer in the surface region of the substrate, growing thereon the epitaxial layer, forming another ion-implanted layer in the surface region of such epitaxial layer, and annealing the substrate so as to diffuse the doped impurity to thereby joint both ion-implanted layers produced by such ion implantations conducted twice. Such method is, however, still disadvantageous in terms of downsizing of the device for the case the vertical diffusion length is considerably large, since such case also requires a sufficient margin for the lateral diffusion. The foregoing patent publication also discloses a technique in which the formation process of a relatively thin epitaxial layer is repeated in plural times, rather than forming a single epitaxial layer which is relatively thick, where the individual formation processes of the epitaxial layers include doping of an impurity in a predetermined region, and perform annealing for diffusion so as to allow the individual impurity-doped regions to overlap with each other from the last epitaxial layer to a desired depth. It is described in the patent publication that such technique is advantageous in that the process only requires a short vertical diffusion length since the ion-implanted layer is provided to every epitaxial layer having a relatively small thickness, which successfully suppresses the lateral diffusion, and shortens the annealing time.
Now in the technique disclosed in the foregoing patent publication, an oxide film formed on the epitaxial layer is used as a mask (referred to as xe2x80x9cion implantation mask oxide filmxe2x80x9d hereinafter) for allowing selective implantation of impurity ion into a specific region in the epitaxial layer. Since the ion implantation mask is formed by thermal oxidation of the surface of the epitaxial layer, so that forming the ion-implanted layer into every epitaxial layer inevitably causes thermal history due to the oxide film formation in the number of repetition same with the number of the epitaxial layers (a first thermal history).
Annealing is also required after the ion implantation in order to recover crystal damage (referred to as xe2x80x9ccrystal recovery annealingxe2x80x9d hereinafter), since crystal damage (defect) inevitably occurs due to the ion implantation effected at a high energy, so that the thermal history due to such annealing will be also added in the number of times same with the repetitive, number of the ion implantation (a second thermal history). In addition, if the surface in the pattern opening exposed after removal by etching of the ion implantation mask oxide film is directly implanted with ion and then annealed for crystal recovery (generally proceeded in an inert atmosphere such as in a nitrogen atmosphere), such surface tends to roughen due to such ion implantation as shown in FIG. 12A. Thus it is a general practice to form, prior to the ion implantation, a thin oxide film for preventing the surface roughening on the surface of the epitaxial layer exposed by the etching as shown in FIG. 12B (so-called pre-implantation oxidation). The formation of such oxide film is accomplished by thermal oxidation, which is again causative of thermal history in the number of times same with the repetitive number of the ion implantation (a third thermal history). Such ion-implanted layer is further stacked with another epitaxial layer grown thereon by the vapor-phase growth process to thereby form a buried layer, where high temperature during the process will be still again causative of thermal history in the number of times same with the repetitive number of epitaxial layers (a fourth thermal history).
Thus in the technique described in the foregoing patent publication, the ion-implanted layers are repetitively affected by four such types of thermal histories in each process cycle comprising the formation of the epitaxial layer and the ion implantation, so that the vertical doped region formed based on such ion-implanted layers cannot always be controlled in terms of diffusion in the lateral direction. For example, as shown in FIG. 6A, for the case that ion-implanted layers 101, 102 are formed between each adjacent epitaxial layers 103a to 103c, diffused regions 101a, 102a already expand to a considerable degree by the time that the formation of the epitaxial layers 103a to 103c and ion-implanted layers 101, 102 is completed due to multiple times of thermal history. If the annealing for diffusion is further proceeded to allow the individual ion-implanted layers 101, 102 to diffuse in the vertical direction and to joint with each other to thereby form a vertical doped region 105, the individual portions 105a, 105b corresponded to the ion-implanted layers 101, 102 will show a large lateral expansion. In particular, the lower ion-implanted layer 101 results in a larger lateral expansion as compared with the upper ion-implanted layer 102, since the former is affected by the repetitive thermal history with a larger number of times.
More specifically, as shown in FIG. 6C, an ion-implanted layer 101 will have a larger degree of the lateral expansion as the position thereof becomes lower, and the layers (in particular in the lower positions) will already be jointed to a certain degree due to the vertical diffusion by the time the top ion-implanted layer is formed. Thus the vertical doped region 105 obtained after the successive annealing will be only such that having a non-uniform width which grows toward the bottom as shown in FIG. 6D. For the case the ion-implanted layers of different conduction types (n-type and p-type, for example) have to be formed in the same epitaxial layer, it is necessary to repeat a process cycle, comprising the formation of the ion implantation mask oxide film, the pre-implantation oxidation and the crystal recovery annealing, for each conduction type, which will worsen the situation.
Another problem resides in the technique disclosed in Japanese Laid-Open Patent Publication 1-105557, in that the multiple repetition of the process cycle, comprising the formation of the ion implantation mask oxide film, the pre-implantation oxidation and the crystal recovery annealing, ruins the productivity due to a large number of the process steps. Beside the foregoing steps, actual process inevitably includes the derivative process steps listed below, which of course further worsen the problem of such low productivity:
(1) pre-oxidation cleaning is necessary before each formation process of the ion implantation mask oxide film in order to remove contaminants and produce a defect-free pattern;
(2) a mark for pattern alignment (so-called an alignment mark) is formed as a stepped or recessed pattern at the same time with the formation of the ion implantation mask, where such solid mark is newly formed each time the epitaxial layer is formed;
(3) a substrate for used in the production of an epitaxial wafer often has a backside oxide film made of silicon dioxide typically grown by the CVD process in order to prevent auto-doping from the side of the major back surface of such substrate. On the other hand on the side of the major front surface of the substrate, the formation and removal of the ion implantation mask oxide film are repeated in plural times on the epitaxial layers. The removal of the oxide film is generally effected by so-called wet etching in which the substrate is immersed into an etching solution such as hydrofluoric acid to thereby chemically dissolve the oxide film, where directly immersing the substrate into an etching solution will also undesirably remove a necessary backside oxide film, so that it is a general practice to form a resist film on the backside oxide film in order to protect thereof. The resist film is, however, not durable at all to the annealing temperature during the formation of the ion implantation mask oxide film, so that it must be removed immediately after the wet etching and must be formed again each time the ion implantation mask oxide film is formed; and
(4) pattern formation on the oxide layer is accomplished by photo-lithography, which is, as known well, include as much as three process steps of exposure of a photoresist, development and wet etching.
The vapor-phase growth of the epitaxial layer for forming the buried layer has a problem of auto-doping to be solved. That is, when the ion-implanted layer is formed, and the epitaxial layer is grown thereon in vapor-phase to thereby convert the ion-implanted layer into a buried layer, lateral auto-doping may sometimes occur from such ion-implanted layer. In such lateral auto-doping, a dopant element once released into the vapor phase is re-introduced into an epitaxial layer growing in the vicinity of the ion-implanted layer, so that even regions not subjected to the ion implantation may consequently be doped, which fails in obtaining target device properties at the interface of the epitaxial layers. A special care should be taken for the case that an n-type buried layer is produced by the ion implantation using, for example, phosphorus (P) which is most causative of the auto-doping.
Now another consideration will be made on the case in which a phosphorus-implanted layer is first formed as an n-type ion implanted layer and a p-type ion-implanted layer is then formed by implanting boron (B). The foregoing pre-implantation oxidation performed prior to the formation of the boron-implanted layer will produce a thin oxide film also on the surface of the phosphorus-implanted layer previously formed. Phosphorus has a large segregation coefficient relative to silicon dioxide, a major component of the oxide film, and tends to segregate in a region in the close vicinity of the major surface of the phosphorus-implanted layer on which the oxide film is grown. If the oxide film in such state is removed and another epitaxial layer is grown thereon in vapor phase, the lateral auto-doping from the phosphorus-implanted layer will become more serious affected by such phosphorus condensed at the major surface.
It is therefore a first subject of the present invention to provide a method capable of quite efficiently producing a silicon epitaxial wafer in which a plurality of epitaxial layers are stacked as being individually interposed with a buried layer and the lateral diffusion of the produced ion-implanted layers is desirably suppressed, and to provide a silicon epitaxial wafer producible by such method. A second suject of the present invention is to provide a method for producing a silicon epitaxial wafer based on the alternative repetition of the ion implantation and formation of the epitaxial layer, in which the number of times of forming a solid mark for use in the pattern alignment can be reduced to thereby facilitate the production processes, and to provide a silicon epitaxial wafer producible by such method. A third subject of the present invention is to provide a method for producing a silicon epitaxial wafer in which the lateral auto-doping from the ion-implanted layer can effectively be suppressed, and to provide a silicon epitaxial wafer producible by such method.
(First Aspect)
A first aspect of the present invention is to solve the foregoing first subject. This relates to a method for producing silicon epitaxial wafer in which an impurity element is introduced by ion implantation to a first epitaxial layer to form an ion-implanted layer, and a second epitaxial layer is stacked thereon by vapor-phase growth to thereby produce a structure having the ion-implanted layer as being buried as a buried layer between the first epitaxial layer and the second epitaxial layer, which comprises:
a mask formation step for forming an ion implantation mask made of a photoresist film directly on the surface of the first epitaxial layer;
an ion implantation step for implanting the ion into the first epitaxial layer having the ion implantation mask formed thereon;
a hydrogen annealing step provided after the ion implantation step and before the vapor-phase growth of the second epitaxial layer; and
a vapor-phase growth step for growing in vapor phase the second epitaxial layer after the hydrogen annealing step.
There are two essential points in the production method according to the first aspect. The first point is that a photoresist film, rather than an oxide film, is used for an ion-implantation mask. That is, an ion-implantation mask made of a photoresist film is formed directly on the first epitaxial layer to be implanted with ion, rather than intentionally forming the oxide film on the surface thereof, where formation of a native oxide naturally occurs on the surface of the epitaxial layer at the room temperature or around will be permissible. The second point is that post-implantation annealing for recovering the crystallinity and for carrier activation is proceeded in a hydrogen atmosphere. Forming the ion implantation mask made of a photoresist film directly on the first epitaxial layer means that neither the formation of the ion implantation mask oxide film nor the pre-implantation oxidation is performed, so that the post-implantation annealing for recovering the crystallinity and carrier activation (which may simply be referred to as xe2x80x9ccrystallinity recovery/activation annealingxe2x80x9d hereinafter) is proceeded while the oxide film is not intentionally formed on the surface of the ion-implanted layer.
Now proceeding such crystallinity recovery/activation annealing under the absence of the oxide film on the surface of the ion-implanted layer in a nitrogen atmosphere according to the conventional practice will enhance the surface roughness of the ion-implanted layer after such annealing. The present inventors, however, found out after extensive investigations that proceeding such crystallinity recovery/activation annealing in a hydrogen atmosphere can quite effectively suppress the surface roughening. This allows, in the method for producing the epitaxial wafer having the buried layers, the pre-implantation oxidation to be omitted, and the ion implantation process to be proceeded using only the photoresist films as the mask. Since there is no need to perform the pre-implantation oxidation or any other processes intentionally forming the oxide film, the present invention can solve every aspect of the conventional problem which possibly arises when the oxide film is used as an ion implantation mask, as described below:
(1) since the oxide film is not used as an ion implantation mask, two of three inevitable thermal histories occurred in the prior art can be avoidable; which are the first thermal history in relation to the oxide film formation for producing an ion implantation mask, and the third thermal history in association to the pre-implantation oxidation. Thus the lateral diffusion of the buried layer and the impurity-doped region formed based thereon can effectively be suppressed;
(2) two process steps for forming the oxide film, that are the step for forming the mask oxide film and for pre-implantation, are omissible: and
(3) omission of the step for forming the mask oxide film also results in omission of the steps for the pre-oxidation cleaning and for removal by etching of the oxide film. Also the steps for forming the resist film for protecting the backside oxide film can totally or partially be omissible.
This dramatically simplifies the production process of the epitaxial wafer having the buried layer, and in particular that having a plurality of epitaxial layers and ion-implanted layers stacked with each other.
The foregoing production method of the present invention can be applicable also to the case the ion-implanted layer patterns differ in the conduction type are formed in the same epitaxial layer, if the method comprises:
a first ion implantation step for implanting ion of the first impurity into the first epitaxial layer having the first ion implantation mask formed thereon, to thereby form a first ion-implanted layer at the position corresponded to the first region;
a second mask formation step for forming a second ion implantation mask, which is for use in ion implantation of a second impurity which differs from the first impurity in a second region which differs from the first region on the surface of a first epitaxial layer, directly on the surface of such first epitaxial layer using a photoresist film;
a second ion implantation step for implanting ion of the second impurity into the first epitaxial layer having the second ion implantation mask formed thereon, to thereby form a second ion-implanted layer at the position corresponded to the second region;
a hydrogen annealing step provided after the second ion implantation step and before vapor-phase growth of a second epitaxial layer on the first epitaxial layer having the first and second ion-implanted layers formed therein; and
a vapor-phase growth step for growing in vapor phase the second epitaxial layer after the hydrogen annealing step, to thereby convert the first ion-implanted layer and the second ion-implanted layer into a first buried layer and a second buried layer, respectively.
In the case the first ion-implanted layer and the second ion-implanted layer are formed in the same the epitaxial layer, using the oxide mask as in the conventional process will require two process cycles comprising oxide film formation, photoresist coating, pattern exposure/development, etching (pattern formation), photoresist removal, ion implantation, and oxide film removal; which are proceeded in this order for each of such two kinds of ion-implanted layers. This requires annealing to be repeated twice for the oxide film formation, which undesirably promotes the diffusion of the doped impurities (in particular in the ion-implanted layer formed earlier). The conventional process also requires etching to be performed twice for each of the pattern formation and oxide film removal, total four times, so that accordingly the photoresist coating for protecting the backside oxide film (backside coating) have to be performed four times.
On the contrary, the method of the present invention not only succeeded in avoiding thermal history accompanied with the oxide film formation, but also in omitting the etching for the pattern formation and the oxide film removal, and in omitting the backside coating; so that entire process is dramatically simplified so as to include the steps only for the photoresist, coating, pattern exposure/development, ion implantation and photoresist removal. Further simplification of the process is expectable since the crystallinity recovery annealing for two kinds of the ion-implanted layers can be effected at the same time.
The production method of the present invention is also applicable to the production of an epitaxial wafer having a plurality of epitaxial layers and buried layers alternately stacked if the process cycle comprising the mask formation steps, the ion implantation steps, the hydrogen annealing step and the vapor-phase growth step is repeated one more time or a plural times, while assuming the second epitaxial layer as a new first epitaxial layer; which results in a plurality of epitaxial layers stacked with each other while being respectively interposed with the buried layer.
According to such method, the thermal histories applied to the individual epitaxial layers are limited to those in association with the heating during the crystallinity recovery/activation annealing in a hydrogen atmosphere after the ion implantation and the heating during the vapor-phase growth, so that the thermal history is less cumulative in the lower buried layers even if a number of epitaxial layers are stacked while being interposed with such buried layers, and thus the thermal histories are respectively applied during the formation of the successive epitaxial layers and buried layers. This successfully reduces difference between degrees of expansion of lower and upper layers, and can effectively suppress the disadvantage that the buried layers in the lower position show larger lateral expansion to thereby ruin the uniformity.
For example, it is advantageous to form the foregoing vertical doped region so that all of the buried layers implanted with the same impurity are separated from each other in the stacking direction of the silicon epitaxial layers. A plurality of such ion-implanted layers can be diffused in the stacking direction of the epitaxial layers (referred to as xe2x80x9cvertical directionxe2x80x9d hereinafter), to thereby joint with each other to produce the foregoing vertical doped region.
The epitaxial wafer of the present invention obtained by such production method is such that for fabricating therein a device having a structure in which a plurality of impurity-doped regions are interconnected in the stacking direction of a plurality of epitaxial layers, wherein a plurality of the epitaxial layers individually have an ion-implanted layer of the same conductivity type buried in the same region. Such constitution, in which the thermal history is less cumulative, can suppress the expansion of the vertically aligned buried layers, so that, all of such buried layers are vertically aligned as being separated from each other. In such constitution, also the lateral expansion of the buried layers is accordingly suppressed, so that the vertical doped region obtained by diffusing and joining these buried layers will be such that having a uniform width only with a small difference in the expansion (or dimension) between the lower layers and the upper layers. This is also exceptionally advantageous in downsizing of semiconductor devices fabricated using such vertical doped region.
(Second Aspect)
A second aspect of the present invention is to solve the foregoing second subject. This relates to a method for producing silicon epitaxial wafer in which a plurality of epitaxial layers are stacked, while being individually interposed with an ion-implanted layer as a buried layer, which is obtained by repeating a set of process steps comprising a step for implanting ion of an impurity element into a first epitaxial layer to thereby form therein an ion-implanted layer, and a step for growing thereon in vapor phase a second epitaxial layer to thereby convert the ion-implanted layer into a buried layer. The method comprises:
a step for forming on a first epitaxial layer a solid alignment mark as a recess or steps;
a step for forming an ion implantation mask for use in the formation of the ion-implanted layer while being aligned with regard to the first epitaxial layer using such solid alignment mark and transferring a pattern thereto; and
a step for forming on the first epitaxial layer a second epitaxial layer so as to produce thereon a copied solid mark in a relieved manner in compliance with the solid alignment mark, and so as to allow such copied solid mark to be used as a new solid alignment mark in a step for forming the next ion-implanted layer.
In such method, the solid alignment mark of the first epitaxial layer as a lower layer is copied at the time the second epitaxial layer is formed as an upper layer to produce a new solid mark, which is now used as a solid alignment mark with regard to the second epitaxial layer. That is, the solid mark is not newly produced in every growth step of the epitaxial layer, so that the number of repetition of forming the solid mark can considerably be reduced, which improves the productivity. More specifically, this allows a method in which the solid mark not being derived from the a solid alignment mark on the underlying epitaxial layer but can serve as a source pattern for forming copied solid marks (referred to as xe2x80x9ctransfer source solid alignment markxe2x80x9d) for the successive epitaxial layers is formed only a part of the layers including the lowermost layer from those having therein the buried layers. In other words, the transfer source solid alignment mark is not formed in the epitaxial layers other than a part of those including the lowermost layer, so that the number or process steps for forming the solid marks can considerably be reduced, which improves the productivity.
The transfer source solid alignment mark can be formed by the wet etching process, or the dry etching process such as ion etching.
A constitution of a silicon epitaxial wafer obtained by such method is understood as follows from the viewpoint of the layers having the transfer source solid alignment mark formed thereon. That is, the silicon epitaxial wafer is such that having a plurality of epitaxial layers individually having a buried layer formed therein stacked with each other, in which only a part of such epitaxial layers including the lowermost layer individually have a transfer source solid alignment mark, which is not derived from a solid alignment mark having a recessed or stepped pattern on the underlying epitaxial layer but can serve as a source pattern for forming copied solid marks for the successive epitaxial layers.
Another possible understanding of the constitution of such silicon epitaxial wafer from the viewpoint of the frequency of appearance of the copied solid marks on the top epitaxial layer is as follows. That is, the silicon epitaxial wafer is such that having a plurality of epitaxial layers individually having a buried layer formed therein stacked with each other, in which the top epitaxial layer has solid alignment marks having a recessed or stepped pattern in the number smaller than the number of epitaxial layers stacked with each other.
In either epitaxial wafer, the epitaxial layers having no transfer source solid alignment mark do not require the foregoing wet etching nor dry etching process, which improves the productivity and the cost efficiency.
It should now be noted that repetitive formation/removal of the oxide film on the surface of the same epitaxial layer in order to form the ion implantation mask or to perform pre-implantation oxidation may decay the surface portion of the epitaxial layer having such solid mark formed thereon due to conversion into the oxide film or removal, which may even result in ruining the original shape of the copied solid mark when a new epitaxial layer is formed thereon. In this case, employing the production method according to the first aspect of the present invention in which the ion implantation mask made of a photo resist film is formed directly on the epitaxial layer will successfully suppress such morphological decay of the solid mark. That is, forming the ion implantation mask using a photoresist film, rather than an oxide film, no more requires repetitive process cycles of the oxide film formation and the removal thereof by etching, and thus the decay of the shape of the solid alignment mark formed in the epitaxial layer hardly occurs. This allows the solid alignment mark in the lower epitaxial layer to be copied to a new epitaxial layer grown thereon, and the copied mark to be used as a new solid alignment mark for the upper epitaxial layer.
Now in the first aspect of the present invention, there is no opportunity to perform wet etching since the pattern formation of the ion-implanted layer does not include a step for etching the oxide film. So that employing dry etching such as ion etching also to the formation of the transfer source solid alignment mark will totally exclude the wet etching process, and accordingly no formation process for forming a resist film for protecting the backside oxide layer will be necessary. This is also beneficial in that generating no waste acidic etching solution, which results in saving costs for waste liquid treatment.
It should now be noted that the description below expresses crystal plane as (hkl) and crystal axis as [hkl] using Miller indices, where the general practice in the nomenclature using Miller indices follows the expressions (i) and (ii) below in which negative sign is placed over the character:
(h{overscore (k)}l)xe2x80x83xe2x80x83(i)
[h{overscore (k)}l]xe2x80x83xe2x80x83(ii)
(where, h, k, lxe2x89xa70)
In this specification, however, the descriptions will follow the expressions (i)xe2x80x2 and (ii)xe2x80x2 shown below for convenience:
(h-kl)xe2x80x83xe2x80x83(i)xe2x80x2
[h-kl]xe2x80x83xe2x80x83(ii)xe2x80x2
When the solid alignment mark is copied to the second epitaxial layer, the obtained copied solid mark may have changes in the profile thereof due to the vapor-phase growth mechanism. Such deformation of the copied solid mark becomes larger as the thickness of the second epitaxial layer to be formed or the number of transference (i.e., the number of stack of the epitaxial layers) increases. Larger deformation in the copied solid mark will result in degraded accuracy in the mask alignment necessary for forming the ion-implanted layer.
The present inventors found out from extensive investigations that, for the case the epitaxial layers are formed on a silicon single-crystalline substrate having (100) crystal orientation, the solid alignment mark is preferably formed so as to have a straight portion aligned in a direction 45 degrees or less away from the [011] or [0-1-1] direction. The transfer source solid mark having such straight portion satisfying such condition is less causative of the deformation of the copied solid mark in the second epitaxial layer formed thereon, and the straight portion is kept well recognizable with a sharp edge. Thus when such copied solid mark is used as a new solid mark for the next patterning, using such derived straight portion for the alignment will successfully improve the alignment accuracy for forming the ion-implanted layer. Even when a significant number of epitaxial layers are stacked on an epitaxial layer having such transfer source solid alignment mark, the copied solid mark is less likely to deform, and thus the number of the epitaxial layers in need of the transfer source solid alignment mark to be formed can be reduced, which is still more effective in reducing the number of process steps.
In this case, thus obtained epitaxial wafer will be such that having on a silicon single-crystalline substrate with (100) crystal orientation a plurality of epitaxial layers stacked thereon, in which the uppermost epitaxial layer has formed thereon a solid alignment mark having a recessed or stepped pattern, and having the straight portion aligned in the direction 45 degrees or less away from the [011] or [0-1-1] direction. Forming the copied solid mark as having such straight portion allows such mark to be less likely to deform, which results in reducing the number of repetition of forming the copied alignment mark and in improving the process efficiency.
The alignment solid mark having the straight portion aligned in the direction out of the above angular range will increase the degree of the deformation of the corresponded straight portion of the copied solid mark formed in compliance therewith, which makes the edge unclear and may adversely affect the precise alignment.
(Third Aspect)
A third aspect of the present invention is to solve the foregoing third subject. This relates to a method for producing silicon epitaxial wafer in which phosphorus is introduced by ion implantation to a first epitaxial layer to form a phosphorus-implanted layer, and a second epitaxial layer is stacked thereon by vapor-phase growth to thereby produce a structure having the phosphorus-implanted layer as being buried as a buried layer between the first epitaxial layer and the second epitaxial layer, which comprises:
an ion implantation step for implanting phosphorus ion into the first epitaxial layer;
an annealing step provided after the ion implantation step and before the vapor-phase growth of the second epitaxial layer, which is proceeded at an annealing temperature ranging from 950 to 1,100xc2x0 C. under the normal pressure;
a capping growth step, provided after the annealing step, for growing in vapor phase a capping epitaxial layer by introducing a silicon source gas under reduced pressure; and
a main growth step for growing in vapor phase the second epitaxial layer on the capping epitaxial layer. The silicon source gas is hydrogen-diluted dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3) or silicon tetrachloride (SiCl4).
In the above method, the phosphorus-implanted layer is formed by ion implantation of phosphorus, annealed at a temperature from 950 to 1,150xc2x0 C., and then two-step growth of the epitaxial layer is proceeded by first growing in vapor phase a capping epitaxial layer for the protection against the auto-doping in a silicon source gas atmosphere under the reduced pressure, and then proceeding the main growth step for growing in vapor phase the second epitaxial layer on the capping epitaxial layer, which can quite effectively suppress the auto-doping of phosphorus.
It has been a general understanding that a higher annealing temperature results in a larger amount of the auto-doping. The present inventors made researches on the auto-doping of phosphorus under the normal pressure within a annealing temperature ranging from 850 to 1,200xc2x0 C., and found that the amount of auto-doping becomes smaller in contrast to the previous knowledge within a temperature range from 950 to 1,100xc2x0 C., where a minimum value was observed at 1,080xc2x0 C. or around.
It is considered that, in a temperature range from 950 to 1,100xc2x0 C. under the normal pressure, phosphorus will cause outward diffusion at a constant volume from the epitaxial layer to the vapor phase, while the amount of re-doping from the vapor phase to the epitaxial layer will decrease. Employing now the annealing temperature ranging from 950 to 1,100xc2x0 C. under the normal pressure can promote the outward diffusion of phosphorus but can suppress the amount of the re-doping into the crystal, so that the phosphorus concentration in the surface region of the phosphorus-doped layer decreases, which provides a situation advantageous for preventing the auto-doping of phosphorus. Growing the capping epitaxial layer in the vapor phase in particular under the supply of a silicon source gas under reduced pressure will also successfully suppress the auto-doping of phosphorus which possibly occurs when the surface of the phosphorus-doped layer is capped. Thus the lateral auto-doping of phosphorus is remarkably suppressed over the entire processes. Reducing the pressure during the annealing or an annealing temperature out of the range from 950 to 1,100xc2x0 C. while the pressure being kept in the normal range, will result in insufficient effects in preventing the lateral auto-doping of phosphorus. Growing the capping epitaxial layer in vapor phase under normal or increased pressure will also result in insufficient effects in preventing the lateral auto-doping of phosphorus. The reason why dichlorosilane, trichlorosilane or silicon tetrachloride is used as a silicon source gas for forming the capping epitaxial layer is that such gas allows the film to grow at a high speed and to thereby shorten the growth period during which the lateral diffusion of phosphorus most tends to occur, which is further advantageous in preventing the lateral auto-doping of phosphorus, and that such silicon source gases are easy to handle. It is now also allowable to use dichlorosilane, trichlorosilane or silicon tetrachloride also for the main growth, which will desirably shorten the growth period required for growing the second epitaxial layer to a desired thickness, and which can omit the changeover operation of the source gases between the steps for forming the capping epitaxial layer and the major growth, which is advantageous in terms of shortening the process time and simplification of the production facility.
Such prevention of the auto-doping of phosphorus can achieve a constitution of the silicon epitaxial wafer for the case a plurality of p-type epitaxial layers are stacked while being interposed at the individual interfaces thereof with a phosphorus-implanted layer. That is, the epitaxial layer can be formed so as to have a value calculated by a formula below is 0.5 or below:
(AHxe2x88x92BH)/AH
where, AH represents the average net carrier concentration in a region of the epitaxial layer having a most stable carrier concentration, and BH represents a lowest net carrier concentration at the interface of the epitaxial layers, both values being observed when the net carrier concentration profile of the epitaxial layer is measured at a position adjacent to the phosphorus-implanted layer and not crossing such phosphorus-implanted layer, and along the thickness of the epitaxial layer so as to cross the interface between the adjacent epitaxial layers. Controlling the value (AHxe2x88x92BH)/AH as 0.5 or below at a position adjacent to the phosphorus-implanted layer can make the lateral distribution of the net carrier concentration more uniform, which accordingly provides a device showing stable and excellent characteristics. The net carrier concentration in the context herein means a difference between the concentrations of majority carrier and minority carrier, and can be obtained typically by converting values of spreading resistance into carrier concentrations.
(Fourth Aspect)
A fourth aspect of the present invention is to solve the foregoing third subject. This relates to a method for producing silicon epitaxial wafer in which a boron-buried layer and a phosphorus buried layer are formed at the same time on a single substrate. The method comprises:
a boron implantation step for implanting boron into a first region in a first epitaxial layer, to thereby form a boron-implanted layer at the position corresponded to the first region;
a phosphorus implantation step for implanting phosphorus into a second region which differs from the first region in the first epitaxial layer, to thereby form a phosphorus-implanted layer at the position corresponded to the second region;
a pre-implantation annealing step for oxidizing the surface of the first epitaxial layer provided before the phosphorus implantation step; and
a vapor-phase growth step for growing in vapor phase a second epitaxial layer on the first epitaxial layer having the boron-implanted layer and the phosphorus-implanted layer formed therein, to thereby convert such boron-implanted layer and such phosphorus-implanted layer into a boron-buried layer and a phosphorus-buried layer, respectively.
In a general method for producing a silicon epitaxial wafer, a step for forming an ion implantation mask oxide film, it is very common to provide a pre-implantation oxidation step or a step for forming an ion implantation mask oxide film in which an oxide film used as a mask is formed. The oxide film in such case is mainly composed of silicon dioxide. When the oxide film is formed on the boron-implanted layer and the phosphorus-implanted layer, boron and phosphorus show different behaviors. That is, boron tends to be incorporated into such oxide film, while phosphorus tends to accumulate in the vicinity of the interface with such oxide film, which is ascribable to difference between the segregation coefficients of boron and phosphorus relative to silicon dioxide. A problem now arises in particular on the order of steps for forming the phosphorus-implanted layer and for forming the oxide film on the epitaxial layer in which such phosphorus-implanted layer is formed. If the phosphorus-implanted layer is formed first, and the pre-implantation oxidation of the surface of the first epitaxial layer, in which the phosphorus-implanted layer is already formed, is then performed prior to the formation of the other ion-implanted layer, phosphorus undesirably migrates toward the interface with the oxide layer, or the surface portion of the phosphorus-implanted layer, which tends to cause the lateral auto-doping of phosphorus during the vapor-phase growth of the second epitaxial layer formed on such first epitaxial layer. On the contrary in the method of the present invention, since the pre-implantation oxidation step is always provided before the phosphorus implantation step, so that it may be an unusual situation that phosphorus is concentrated at the surface portion of the phosphorus-implanted layer before the second epitaxial layer is grown, which effectively suppresses the lateral auto-doping of phosphorus.
In an exemplary case in which the phosphorus-implanted layer is first formed in an epitaxial layer, and the boron-implanted layer is then formed in the same epitaxial layer, performing the pre-implantation oxidation before forming the boron-implanted layer will inevitably form the oxide film also on the surface of the phosphorus-implanted layer previously formed. Now performing the phosphorus implantation step after the boron implantation step can successfully avoid the situation that the pre-implantation oxidation before the boron implantation precedes the phosphorus implantation, which is beneficial in avoiding the lateral auto-doping of phosphorus. It is still more preferable that the pre-implantation oxidation is performed even before the boron implantation, since the surface roughening of the epitaxial layer possibly occurs during the boron implantation is avoidable.
After the ion-implanted layer is formed, annealing is generally performed in order to recover the crystal damage generated during the ion implantation. In place of separately performing such annealing after the phosphorus implantation, performing the annealing before the vapor-phase growth of the second epitaxial layer so as to recover the crystal damage generated during the ion implantation is more advantageous in preventing the lateral auto-doping of phosphorus, and can prevent excessive spreading of the buried layer due to thermal diffusion. The crystal damage can also be recovered by thermal history applied during the vapor-phase growth of the second epitaxial layer, or by the thermal diffusion process provided after the formation of the second epitaxial layer (for example, a process for forming the foregoing vertical doped region).
(Fifth Aspect)
A fifth aspect of the present invention is also to solve the foregoing third subject, and is applicable in any combinations with the foregoing first to fourth aspects (or sixth or seventh aspect described later). The method is such that producing a silicon epitaxial wafer in which a plurality of epitaxial layers individually having an ion-implanted layer of the same conductivity type formed as being buried in the same region are stacked with each other, wherein elements to be implanted are boron and phosphorus, and a ratio of the amounts of dose of boron and phosphorus to be implanted in the same epitaxial layer is controlled so as to be inversely proportional to a ratio of the implantation pattern areas of boron and phosphorus. The implantation pattern area of phosphorus is preferably 3 to 10 times that of boron. The amount of dose of phosphorus is preferably ⅓ to {fraction (1/10)} of that of boron.
Such production method can produce a silicon epitaxial wafer having a structure in which a plurality of impurity-doped regions are interconnected in the stacking direction of a plurality of epitaxial layers; a plurality of such epitaxial layers individually have an ion-implanted layer of the same conductivity type buried in the same region; element to be implanted are boron and phosphorus; and a ratio of the amounts of dose of boron and phosphorus to be implanted in the same epitaxial layer is controlled so as to be inversely proportional to a ratio of the implantation pattern areas of boron and phosphorus.
In an exemplary case in which boron and phosphorus are individually implanted into the same epitaxial layer in the same implantation pattern area and at the same amounts of dose, phosphorus will cause auto-doping in an amount 3 to 10 times larger than that of boron if an epitaxial layer is grown by vapor phase deposition so as to bury the implanted layers. Such difference in the amount of auto-doping emphasizes the lateral auto-doping of phosphorus in the vicinity of the interface of the epitaxial layers.
If the amounts of auto-doping of phosphorus and boron can be equalized, the lateral auto-doping from the ion-implanted layer can effectively be suppressed since both impurities will cancel with each other. Thus the amounts of auto-doping of phosphorus and boron are measured in a preliminary study, and the implantation pattern areas and the amounts of dose for both impurities are determined so as to equalize the amounts of auto-doping thereof.
That is, based on a proportional relation between the amount of auto-doping and the surface impurity concentration of the ion-implanted layer, the implantation pattern area for phosphorus showing a larger auto-doping is set 3 to 10 times that for boron, and the amount dose of phosphorus is set ⅓ to {fraction (1/10)} of that for boron. This can reduce the amount of auto-doping of phosphorus while keeping the total amount of implantation thereof unchanged, so that a uniform distribution of doped impurity concentration can be achieved in the vicinity of the interface between the epitaxial layers.
(Sixth Aspect)
A sixth aspect of the present invention is effective in achieving a uniform concentration distribution in the obtained vertical doped region, and is applicable in any combinations with the foregoing first to fifth aspects (or a seventh aspect described later). The method is such that producing a silicon epitaxial wafer in which a plurality of epitaxial layers individually having an ion-implanted layer of the same conductivity type formed as being buried in the same region are stacked with each other, wherein the ion-implanted layers are formed so that a lower one have a higher concentration of the implanted impurity. A silicon epitaxial wafer obtained by the method is such that for fabricating therein a device having a structure in which a plurality of impurity-doped regions are interconnected in the stacking direction of a plurality of epitaxial layers, wherein a plurality of the epitaxial layers individually have an ion-implanted layer of the same conductivity type buried in the same region, and the ion-implanted layers are formed so that the layer in a lower position will have a higher concentration of the implanted impurity.
For the case of forming a structure in which a plurality of epitaxial layers individually having an ion-implanted layer of the same conductivity type formed as being buried in the same region are stacked with each other, an essence of this aspect resides in that forming the ion-implanted layers so that a lower one have a higher concentration of the implanted impurity. An ion-implanted layer in a lower position is affected by repetitive annealing for the formation of the overlying epitaxial layer(s), ion-implanted layer(s) and oxide film(s), and thus tends to cause expansion due to thermal diffusion and tends to lower the impurity concentration. Thus as shown in FIGS. 28A to 28C, ion-implanted layers 250 to 252 are formed so that the lower epitaxial layer among epitaxial layers 103a to 103c stacked with each other, in other words an epitaxial layer formed earlier, will have a higher concentration of the doped impurity. This can reduce the differences among the concentration of implanted impurity of buried layers 250xe2x80x2, 251xe2x80x2 and 252xe2x80x2 aligned in the direction of the stacking of the epitaxial layers 103a to 103d, as shown in FIG. 28D. That is, assuming the individual concentrations of ion implantation for the ion-implanted layers 250 to 252 as C1, C2 and C3, respectively, a relation expressed by C1 greater than C2 greater than C3 is satisfied. This can be achieved by increasing the amount of dose of implanted ion as the position of the epitaxial layer in the stack descends.
The ion-implanted layers 250 to 252 are formed herein so that a lower one has a smaller pattern area. That is, assuming the pattern areas for the ion-implanted layers 250 to 252 as S1, S2 and S3, respectively, a relation expressed by S1 less than S2 less than S3 is satisfied. Accordingly the differences among the pattern area of the buried Blayers 250xe2x80x2, 251xe2x80x2 and 252xe2x80x2 can also be reduced as shown in FIG. 28D.
For example, for the case that the buried layers are formed in a number of three as described in the above while assuming the amounts of dose in the ion implantation for forming such layers as D1, D2 and D3, respectively, such amounts of dose are preferably set so that a relation expressed by an equation below is satisfied from the viewpoint of reducing the differences among the impurity concentrations of the buried layers 250xe2x80x2, 251xe2x80x2 and 252xe2x80x2:
D1:D2:D3=(S2/S1)2xc3x97C2:C2:(S2/S3)2xc3x97C2
Such relation between the amount of dose and the pattern area is applicable also to the case the buried layers are formed in a number of three. Thus the vertical doped region obtained by diffusing such buried layers by annealing is uniform not only in the impurity concentration but also in the axial sectional area, which can, for example, improve the integration density of devices fabricated using such vertical doped region.
(Seventh Aspect)
This aspect of the present invention can be combined with any one of the foregoing aspects 1 to 6, or effected independently therefrom. This relates to a method for fabricating a silicon epitaxial wafer in which a plurality of epitaxial layers are stacked with each other while being individually interposed with an ion-implanted layer, by repeating a set of process steps comprising:
a first vapor phase deposition step for growing in vapor phase first epitaxial layer;
a first ion implantation step for implanting ion of a first impurity element into a first region in the surface portion of the first epitaxial layer, to thereby form a first ion-implanted layer;
a second vapor phase deposition step for growing in vapor phase a second epitaxial layer after the first ion implantation step; and
a second ion implantation step for implanting ion of a second impurity element into a second region which differs from the first region in the surface portion of the first epitaxial layer, to thereby form a second ion-implanted layer at the position corresponded to such second region;
so as to form all of the first ion-implanted layers and all of the second ion-implanted layers are respectively formed in the same region, and so as to stagger the first and second ion-implanted layers.
A specific embodiment is shown in FIGS. 29A to 29C. In this embodiment, an epitaxial layers 103 are stacked while being interposed with a boron-implanted layer 71 as the first ion-implanted layer and a phosphorus-implanted layer 72 as the second ion-implanted layer, where both layers 71, 72 being staggered. As described in the above, there is a large difference between boron and phosphorus in the lateral auto-doping behavior, and growth conditions for the epitaxial layers allowing such difference to be minimized also differ. For the case such two kinds of impurities which differ in the lateral auto-doping behavior are implanted into the same epitaxial layer, a growth condition for growing thereon the second epitaxial layer will suffer from a contradiction that a condition optimum for one impurity in terms of suppressing auto-doping is not advantageous for the other. Even though a compromising condition for both impurities is employed, the conditions remain as being not optimized in terms of suppressing the lateral auto-doping. Employing now the method of the present invention allows the growth conditions for minimizing the lateral auto-doping of one impurity can be determined independently from that for the other for each epitaxial layer, since each epitaxial layer has only either one of the first ion-implanted layer and the second ion-implanted layer. This effectively suppresses the lateral auto-doping of both buried layers having the individual impurities.
When thus-obtained silicon epitaxial wafer is subjected to the annealing, the ion-implanted layers formed in the individual epitaxial layers are mutually joined in the stacking direction of such epitaxial layers, to thereby produce a plurality of vertical impurity doped regions (a vertical boron-doped region 171 and a vertical phosphorus-doped region 172, herein) as shown in FIG. 29E. Characteristics of such wafer are as follows. There are formed the boron-doped region 171 doped with boron (first impurity) and the phosphorus-doped region 172 doped with phosphorus (second impurity), where both of which respectively have minimum diameter portions 171b, 172b and maximum diameter portions 171a, 172a alternately aligned along an axial direction which coincides with the stacking direction of the epitaxial layers 103, to thereby have a corrugated columnar form. These boron-doped region 171 and the phosphorus-doped region 172 individually have staggered periodicities of formation of such minimum diameter portions 171b, 172b and maximum diameter portions 171a, 172a, wherein the maximum diameter portions 171a, 172a of either one and the minimum diameter portions 171b, 172b of the other are aligned at the same level, respectively. This allows the inter-axial distance between the boron-doped region 171 and the phosphorus-doped region 172 to be narrowed, to thereby increase the integration density of devices fabricated by using such impurity-doped regions 171, 172.
In such case, if the adjacent boron-doped region 171 and the phosphorus-doped region 172 are formed so that the maximum diameter portions 171a, 172a thereof are partially overlapped in the plan view, that is in other words, if a projected portion of one doped region having a larger diameter is aligned so as to come into a recessed portion of the other doped region having a small diameter, the inter-axial distance between the boron-doped region 171 and the phosphorus-doped region 172 can further be narrowed, which further enhances the foregoing effect. In such case, a first ion-implanted layer 71 and the second ion-implanted layer 72 adjacent as being interposed by the epitaxial layer 103 are formed so as to partially overlap with each other when viewed from the stacking direction of such epitaxial layers 103. More specifically, the first ion-implanted layers 71 and the second ion-implanted layers 72 always formed in the same epitaxial layer as shown in FIG. 30A give an outer dimension xe2x80x9cAxe2x80x9d, and the first ion-implanted layers 71 and the second ion-implanted layers 72 formed alternately in the adjacent epitaxial layers in a partially overlapped manner as shown in FIG. 30A give an outer dimension xe2x80x9cBxe2x80x9d, which can be reduced as much as by approx. 6% from xe2x80x9cAxe2x80x9d.
(Eighth Aspect)
An eighth aspect of the present invention relates to a method for producing a silicon epitaxial layer, which can be corresponded to a combination of the first and third aspects (where a source gas for forming the epitaxial layers are not limited to trichlorosilane, and an impurity is not limited to phosphorus). The method is such that producing a silicon epitaxial wafer in which a plurality of epitaxial layers are stacked, while being individually interposed with an ion-implanted layer as a buried layer, by repeating a set of process steps comprising:
a first vapor-phase growth step for growing vapor phase a first epitaxial layer on a silicon single-crystalline substrate having a major front surface of (100) crystal orientation;
a first mask formation step for forming a first ion implantation mask, which is for use in ion implantation of a first impurity in a first region on the surface of the first epitaxial layer, directly on the surface of such first epitaxial layer using a photoresist film;
a first ion implantation step for implanting ion of the first impurity into the first epitaxial layer having the first ion implantation mask formed thereon, to thereby form a first ion-implanted layer at the position corresponded to the first region;
a second mask formation step for forming a second ion implantation mask, which is for use in ion implantation of a second impurity which differs from the first impurity in a second region which differs from the first region on the surface of a first epitaxial layer, directly on the surface of such first epitaxial layer using a photoresist film;
a second ion implantation step for implanting ion of the second impurity into the first epitaxial layer having the second ion implantation mask formed thereon, to thereby form a second ion-implanted layer at the position corresponded to the second region;
a hydrogen annealing step provided after the second ion implantation step, which is proceeded at an annealing temperature ranging from 950 to 1,100xc2x0 C. under the normal pressure; and
a capping growth step, provided after said hydrogen annealing step, for growing in vapor phase a capping epitaxial layer under reduced pressure as a lot,
stackingly forming several epitaxial layers, by the repetition of two or more groups of those steps, in the form by which ion-implantation layers are sandwiched as buried layers between layers.
A specific feature now resides in that the hydrogen annealing step provided after the second ion implantation step, which is proceeded at an annealing temperature ranging from 950 to 1,150xc2x0 C. under the normal pressure, also serves as the annealing in the third aspect. Growing in vapor phase the capping epitaxial layer under reduced pressure after the hydrogen annealing ensures not only various effects of the first aspect, but also the effect of the third aspect which relates to the effective suppression of the lateral auto-doping of phosphorus.
In the above method, the effect of the second aspect is also obtainable if the solid alignment mark is formed so as to have a straight portion comprising a recessed or stepped portion and aligned in a direction 45 degrees or less away from the [011] or [0-1-1] direction. It is still also possible to obtain the effect of the fifth aspect if the ion-implanted layers are formed so that the layer in a lower position will have a higher dosage and a smaller pattern area.